The United States Government has rights in this invention pursuant to Contract No. W-7405-ENG-48 between the U.S. Department of Energy and the University of California, for the operation of Lawrence Livermore National Laboratory.
The invention relates generally to integrated circuit fabrication, and more particularly to the interconnection of chips mounted on a substrate and methods of forming the interconnects.
One problem in manufacturing hybrid wafer scale integration (HWSI) circuits is making interconnections between the various chips after they have been attached to a common substrate. The speed and compactness of modern electronic systems containing many integrated circuit (IC) chips are often compromised by the methods used to package and interconnect these chips. Ideally, chip-to-chip interconnects should have very high density (e.g. at least 1000 connections on a 1-cm square chip) but very low inductance, capacitance, and resistance. Multi-layer ceramic (MLC) interconnection modules, onto which many unpackaged IC chips can be mounted, partly address these needs but are limited and expensive. The manufacturing processes limit the minimum geometry of MLC interconnects to rather coarse dimensions (about 250 .mu.m pitch). Thus, a very large number of metal layers (as many as 33) is required to provide dense interconnect, power distribution and crosstalk isolation. Other difficulties include thermal expansion mismatch (4.times.10.sup.-6 /.degree.C. difference between Si and alumina), high dielectric constant (about 9.4 for alumina) with consequent low signal propagation speeds, and substantial thermal resistance of the relatively thick ceramic (typically 2 cm.sup.2 -.degree.C./W).
To overcome limitations and expense of MLC technology for high-performance systems, silicon wafers can be used as substrates for thin-film interconnection modules. These silicon PC boards (SiPCBs) can provide very precise, high-density interconnects with a minimal number (3 or 4) of metal levels. With sufficient metallization thickness (about 5 .mu.m), transmission-line quality interconnects are achievable over wafer-scale distances (about 20 cm). SiPCBs have outstanding thermal and mechanical characteristics; compact liquid-cooled versions can dissipate a heat flux of more than 1000 W/cm.sup.2, and they are virtually immune to thermal stresses, owing to the thermal expansion match between the chips and the board.
In order to physically attach and then electrically connect IC chips to a silicon wafer, three standard techniques have been successfully adapted from ceramic hybrid technology: flip-chip solder-bump reflow, wire bonding, and tape-automated bonding (TAB). All use macroscopic solder joints or welds to make the electrical connections between chip and module, which are ultimately subject to fatigue failures induced by thermal cycling. An interconnect method which provides low inductance, high interconnection density, high reliability and backside bonding (for heat conduction) is desired; however, none of the prior art methods provide a combination of all these characteristics. Flip-chip technology can provide a fairly dense array of low-inductance (&lt;0.1 nH) interconnects, but has poor heat transfer (elaborate measures are required to dissipate even a 20 W/cm.sup.2 heat flux), and requires extra metallization levels for routing to bond pads and for metallurgical reasons. Electrical contact to the back side of the substrate is poor or nonexistent, which is a problem for certain technologies such as power devices or radiation-hardened CMOS. In contrast, wire-bonding and TAB both permit the chip back side to be rigidly attached to a substrate, which enables much better thermal and electrical contact to the interconnection module. However, both have enough inductance (&gt;2 nH for typical 2.5-mm long bonds) to cause problems in ultra-high speed digital or microwave applications, and both are limited in density.
Thus, chip-to-board interconnection technology appears to be a weak point in terms of electrical performance and mechanical reliability of silicon hybrid WSI technology. A thin-film interconnection technique might provide substantially greater interconnect density (e.g., at least a 50 .mu.m pitch and preferably a 25 .mu.m pitch), with excellent electrical properties (impedance-matched transmission lines, if desired), while enhancing the reliability of the connections by replacing the solder/weld joints with standard thin-film contacts.